1. Field of the Invention
The present invention relates to static timing analysis (STA) and in particular to efficient data compression for vector-based static timing analysis.
2. Related Art
Large capacity and computation demands can be major bottlenecks in vector-based STA. In current deep submicron technologies, the timing performance of integrated circuits (ICs) is subject to significant process, voltage, and temperature variations. Multi-corner analysis continues to remain a commonly-adopted standard for sign-off quality STA.
Instead of running multiple STA at different corners, an efficient method may perform multi-corner analysis in a single vector-based STA, wherein vectors represent timing responses at multiple corners. More generally, each condition (i.e. a corner or mode) can correspond to one data point in the vector. Alternatively, Monte-Carlo based statistical STA (SSTA) can cover multiple corners in a single analysis. Due to the increasing amount of corners and modes, processing large vector data or statistical data can result in a prohibitive memory footprint.
Moreover, although the resulting data can be compressed using any manner of compression techniques, the processing of the data currently requires decompression of that data. Because data are typically accessed multiple times during processing while still trying to minimize the memory footprint, the data are repeatedly compressed and decompressed, thereby resulting in prohibitive runtime overhead.
Therefore, a need arises for efficient methods to reduce memory and runtime for applications of vector-based STA and SSTA associated with large-scale ICs.